The truth behind the beauty is a bit more elusive however. In fact, there are only a handful of testimonials available as yet to confirm the unified flow claims, and those testimonials are riddled with alpha-this and beta-that. Cadence has got its Integration Ensemble, positioned within its more long-term Super Chip

Initiative. Synopsys has got its Physical Compiler walking in lock-step with Design Compiler, and a lot of Chip Architect and friends packaged along the way between the front and back end. Avanti's got its Single Pass-SOC and Astro and Columbia and Venus. Certainly, Magma's announcement at last year's DAC plays in this same league if only for similar levels of brash and bravado. And this is not to pick on any of these guys, not to throw stones at their efforts just because they've been gutsy enough to try to get the thing thought through and packaged for resale.

Clearly, these tool suites are not complete.

They haven't been fully exercised. They're new. They need time. But the work won't wait; chips need to be designed, taped-out, and manufactured even as we speak.

It seems that, for the sake of the designers, it would be great to see a benchmark happen-and it should be something a tad more scientific than amateur poll-taking by the Industry Gadfly from ESNUG.

I've been told that asking for a benchmark for the unified flow is simplistic thinking. But, how much more simplistic is it than some of the marketing language being used to position these design suites? Would a benchmark help designers know if they can just put down their current toys and pick up the new ones and be done? How much of a fantasy is it to want to see a real design-let's say one of those trendy SOCs complete with microprocessors, I/Os, memory, digital, analog, and mixed-signal-put these tool suites through their paces? A number of people in the know have told me that a benchmark is the stuff of fairy tales, too hard to pull it off, technically not feasible. It might be a fairy tale, but Beauty and the Benchmark would make a great read.

Meanwhile, there's an even more profound question for those who hope to craft the complex designs skulking about in the fevered imaginations of customers today who want zillions of functions planted perfectly-with minimum cost-on a single, fertile piece of silicon. These design monsters are not going to be sorted out between the RTL and the GDSII. They're going to need more-lots more. They're going to need system-level design languages, tools, and methodologies-and the greatest of these is methodologies.

So, in truth, the benchmark really needs to move upstream, to much higher levels of abstraction than a garden-variety RTL-to-GDSII exercise. With so much hanging in the balance, so many parameters running loose, this system-level benchmark is way beyond the level of rational thought. In fact, it exceeds the confines of fairy tale, and moves right into the realm of epic mythology, something best titled Benchmark and the Beast.